Lowering supply voltage, VDD> is the most effective means to reduce power dissipation of CMOS LSI design. In low VDD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage, V th, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to low Vth, while the second approach degrades worst case circuit speed caused by Vth fluctuation in low VDD. This paper presents two circuit techniques to solve these problems, in both of which Vth is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raises Vth in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reduces Vth fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 V VDD.
|ジャーナル||Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology|
|出版ステータス||Published - 1996 1月 1|
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