TY - GEN
T1 - Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs
AU - Ota, Kensuke
AU - Saitoh, Masumi
AU - Nakabayashi, Yukio
AU - Ishihara, Takamitsu
AU - Numata, Toshinori
AU - Uchida, Ken
PY - 2010
Y1 - 2010
N2 - Threshold voltage shift and drain current degradation by NBT stress in Si (100) and (110) pMOSFETs are systematically studied. Threshold voltage shift in (110) pFET is larger than that in (100) pFET. However, time and temperature dependence of NBTI suggest that the mechanisms of the NBTI degradation are independent of the surface orientations. It is newly found that the drain current degradation in (110) pFET is severer than that in (100) pFET even when the same amount of charges at the interface is generated. This can be explained by larger mobility degradation in (110) pFETs due to the generated interface traps.
AB - Threshold voltage shift and drain current degradation by NBT stress in Si (100) and (110) pMOSFETs are systematically studied. Threshold voltage shift in (110) pFET is larger than that in (100) pFET. However, time and temperature dependence of NBTI suggest that the mechanisms of the NBTI degradation are independent of the surface orientations. It is newly found that the drain current degradation in (110) pFET is severer than that in (100) pFET even when the same amount of charges at the interface is generated. This can be explained by larger mobility degradation in (110) pFETs due to the generated interface traps.
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U2 - 10.1109/ESSDERC.2010.5618447
DO - 10.1109/ESSDERC.2010.5618447
M3 - Conference contribution
AN - SCOPUS:78649929786
SN - 9781424466610
T3 - 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
SP - 134
EP - 137
BT - 2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
T2 - 2010 European Solid State Device Research Conference, ESSDERC 2010
Y2 - 14 September 2010 through 16 September 2010
ER -