TY - JOUR
T1 - Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme
AU - Hamada, Mototsugu
AU - Takahashi, Masafumi
AU - Arakida, Hideho
AU - Chiba, Akihiko
AU - Terazawa, Toshihiro
AU - Ishikawa, Takashi
AU - Kanazawa, Masahiro
AU - Igarashi, Mutsunori
AU - Usami, Kimiyoshi
AU - Kuroda, Tadahiro
PY - 1998/1/1
Y1 - 1998/1/1
N2 - A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.
AB - A novel design technique which combines a Variable Supply-voltage scheme and a Clustered Voltage Scaling is presented (VS-CVS scheme). A theory to choose the optimum supply voltages in the VS-CVS scheme is discussed which enables us to perform chip design in a top-down fashion. Level-shifting flip-flops are developed which reduce power, delay, area penalties significantly. Application of this technique to an MPEG4 video codec saves 55% of the power dissipation without degrading circuit, performance compared to a conventional CMOS design.
UR - http://www.scopus.com/inward/record.url?scp=0031634512&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0031634512&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0031634512
SN - 0886-5930
SP - 495
EP - 498
JO - Proceedings of the Custom Integrated Circuits Conference
JF - Proceedings of the Custom Integrated Circuits Conference
T2 - Proceedings of the 1998 IEEE Custom Integrated Circuits Conference
Y2 - 11 May 1998 through 14 May 1998
ER -