An over 1 Tb/s scalable ATM switching system architecture is proposed suitable for the mature B-ISDN environment. Two kinds of switch modules are combined, the small-scale switch with VC and VP-level management named AHM having 10 to 20 Gb/s throughput, and the high-speed and simple routing switch named AMC offering simple ATM layer management for AHMs-interconnection. AMC resource management employs the Grouped VP resource management scheme only at AHM. The proposed system architecture gives high statistical multiplexing gain from small-size switches to over 1 Tb/s switches and easy management; switching capacity can be efficiently expanded. As the switch architecture of the AMC, a high-speed and scalable ATM switch architecture, named TORUS-switch, is proposed. The switch is an internal speed-up crossbar-type switch with cylindrical configuration. The self-bit-synchronization technique is adopted to achieve high-speed cell transmission without requiring high-density implementation technology. Also, distributed contention-control based on the fixed output-precedence scheme is newly adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultra-high-speed crosspoint LSI using the advanced Si-bipolar process to confirm its feasibility. Measured results confirm that the TORUS-switch can be used to realize a expandable tera-bit-rate ATM switch that is also efficient.
|出版ステータス||Published - 1995 12月 1|
|イベント||Proceedings of the 1995 IEEE Global Telecommunications Conference. Part 2 (of 3) - Singapore, Singapore|
継続期間: 1995 11月 14 → 1995 11月 16
|Other||Proceedings of the 1995 IEEE Global Telecommunications Conference. Part 2 (of 3)|
|Period||95/11/14 → 95/11/16|
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