Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Weihan Wang; Yuya Ohta; Yoshifumi Ishii; Kimiyoshi Usami; Hideharu Amano

doi:10.1109/COOLChips.2012.6216587

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano

情報工学科

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28∼54% at 25C.

本文言語	English
ホスト出版物のタイトル	Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV
DOI	https://doi.org/10.1109/COOLChips.2012.6216587
出版ステータス	Published - 2012 7月 25
イベント	15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV - Yokohama, Japan 継続期間: 2012 4月 18 → 2012 4月 20

出版物シリーズ

名前	Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

Other

Other	15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV
国/地域	Japan
City	Yokohama
Period	12/4/18 → 12/4/20

ASJC Scopus subject areas

コンピュータネットワークおよび通信

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10.1109/COOLChips.2012.6216587

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引用スタイル

Wang, W., Ohta, Y., Ishii, Y., Usami, K., & Amano, H. (2012). Trade-off analysis of fine-grained power gating methods for functional units in a CPU. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV Article 6216587 (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV). https://doi.org/10.1109/COOLChips.2012.6216587

Wang, W, Ohta, Y, Ishii, Y, Usami, K & Amano, H 2012, Trade-off analysis of fine-grained power gating methods for functional units in a CPU. in Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV., 6216587, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV, 15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV, Yokohama, Japan, 12/4/18. https://doi.org/10.1109/COOLChips.2012.6216587

@inproceedings{1a783b38ce75449384622e8ea0710427,

title = "Trade-off analysis of fine-grained power gating methods for functional units in a CPU",

abstract = "High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28∼54% at 25C.",

keywords = "Leakage Power and Processor, Power Gating",

author = "Weihan Wang and Yuya Ohta and Yoshifumi Ishii and Kimiyoshi Usami and Hideharu Amano",

year = "2012",

month = jul,

day = "25",

doi = "10.1109/COOLChips.2012.6216587",

language = "English",

isbn = "9781467312028",

series = "Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV",

booktitle = "Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV",

note = "15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV ; Conference date: 18-04-2012 Through 20-04-2012",

}

TY - GEN

T1 - Trade-off analysis of fine-grained power gating methods for functional units in a CPU

AU - Wang, Weihan

AU - Ohta, Yuya

AU - Ishii, Yoshifumi

AU - Usami, Kimiyoshi

AU - Amano, Hideharu

PY - 2012/7/25

Y1 - 2012/7/25

N2 - High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28∼54% at 25C.

AB - High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28∼54% at 25C.

KW - Leakage Power and Processor

KW - Power Gating

UR - http://www.scopus.com/inward/record.url?scp=84864074147&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84864074147&partnerID=8YFLogxK

U2 - 10.1109/COOLChips.2012.6216587

DO - 10.1109/COOLChips.2012.6216587

M3 - Conference contribution

AN - SCOPUS:84864074147

SN - 9781467312028

T3 - Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

BT - Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

T2 - 15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV

Y2 - 18 April 2012 through 20 April 2012

ER -

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

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