TY - JOUR
T1 - Two Step Timing Synchronization Scheme for OFDM Signal in General Purpose Processor Based Software Defined Radio Receiver
AU - Tanaka, Yuki
AU - Inamori, Mamiko
AU - Sanada, Yukitoshi
N1 - Funding Information:
Acknowledgments This work is supported in part by a Grant-in-Aid for Scientific Research (C) under Grant No.25426382 from the Ministry of Education, Culture, Sports, Science, and Technology of Japan.
Publisher Copyright:
© 2014, Springer Science+Business Media New York.
PY - 2014/10/22
Y1 - 2014/10/22
N2 - Software defined radio (SDR) is a technology that allows a single terminal to support various kinds of wireless systems by changing its software to reconfigure itself. A general purpose processor (GPP) based SDR receiver platform named Sora has been recently developed by Microsoft. In the GPP based SDR receiver, timing synchronization of an OFDM signal consumes a significant amount of computational resources in the GPP. In this paper, a timing synchronization scheme which uses delayed correlation and matched filtering for the GPP based SDR platform is evaluated. The two stage timing synchronization scheme reduces the computational complexity by limiting the timing range of matched filtering. The proposed scheme reduces the amount of data transmission between the memory and the GPP of the SDR platform. It is shown through an experiment that the proposed scheme reduces the number of cycles for timing synchronization by up to 30 %.
AB - Software defined radio (SDR) is a technology that allows a single terminal to support various kinds of wireless systems by changing its software to reconfigure itself. A general purpose processor (GPP) based SDR receiver platform named Sora has been recently developed by Microsoft. In the GPP based SDR receiver, timing synchronization of an OFDM signal consumes a significant amount of computational resources in the GPP. In this paper, a timing synchronization scheme which uses delayed correlation and matched filtering for the GPP based SDR platform is evaluated. The two stage timing synchronization scheme reduces the computational complexity by limiting the timing range of matched filtering. The proposed scheme reduces the amount of data transmission between the memory and the GPP of the SDR platform. It is shown through an experiment that the proposed scheme reduces the number of cycles for timing synchronization by up to 30 %.
KW - General purpose processors
KW - IEEE802.11g
KW - OFDM
KW - Software defined radio
KW - Timing synchronization
UR - http://www.scopus.com/inward/record.url?scp=84910019994&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84910019994&partnerID=8YFLogxK
U2 - 10.1007/s11277-014-1860-6
DO - 10.1007/s11277-014-1860-6
M3 - Article
AN - SCOPUS:84910019994
SN - 0929-6212
VL - 79
SP - 363
EP - 374
JO - Wireless Personal Communications
JF - Wireless Personal Communications
IS - 1
ER -