TY - JOUR
T1 - Utilizing surplus timing for power reduction
AU - Hamada, Mototsugu
AU - Ootaguro, Yukio
AU - Kuroda, Tadahiro
PY - 2001/1/1
Y1 - 2001/1/1
N2 - Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.
AB - Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.
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U2 - 10.1109/CICC.2001.929730
DO - 10.1109/CICC.2001.929730
M3 - Article
AN - SCOPUS:0034837915
SN - 0886-5930
SP - 89
EP - 92
JO - Proceedings of the Custom Integrated Circuits Conference
JF - Proceedings of the Custom Integrated Circuits Conference
ER -