Variable supply-voltage scheme for low-power high-speed CMOS digital design

Tadahiro Kuroda; Kojiro Suzuki; Shinji Mita; Tetsuya Fujita; Fumiyuki Yamane; Fumihiko Sano; Akihiko Chiba; Yoshinori Watanabe; Koji Matsuda; Takeo Maeda; Takayasu Sakurai; Tohru Furuyama

doi:10.1109/4.661211

Variable supply-voltage scheme for low-power high-speed CMOS digital design

Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama

研究成果: Article › 査読

204 被引用数 (Scopus)

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This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

本文言語	English
ページ（範囲）	454-461
ページ数	8
ジャーナル	IEEE Journal of Solid-State Circuits
巻	33
号	3
DOI	https://doi.org/10.1109/4.661211
出版ステータス	Published - 1998 3月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.661211

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AU - Suzuki, Kojiro

AU - Mita, Shinji

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AU - Yamane, Fumiyuki

AU - Sano, Fumihiko

AU - Chiba, Akihiko

AU - Watanabe, Yoshinori

AU - Matsuda, Koji

AU - Maeda, Takeo

AU - Sakurai, Takayasu

AU - Furuyama, Tohru

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Variable supply-voltage scheme for low-power high-speed CMOS digital design

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