The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.
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