Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate

This work clarifies the warpage and thermal stress under thermal cycling test (TCT) by 3D multi-physics solver for SiC and Si power device chip systems using direct Ag sintering chip-attachment on Cu plate. We compare the simulated warpages to the warpage results measured at room temperature for SiC/Si test structures. Measured warpages were in good agreement with our simulation values, and the simulation accuracy at Cu thickness of 1 mm was within 10 percentages for SiC structure. It was also found that the warpage in SiC structure is considerably larger than that in Si structure due to larger Young's modulus of SiC. Our simulations also showed that the warpage and displacement difference become smaller, and the thermal stress becomes stronger as the Cu plate thickness increases for both SiC/Si structures. The simulated maximum stress values under TCT decrease as Ta increases and approaches the stress free temperature. It was found that thermal stress values do not vary linearly with Ta. This nonlinearity is thought to be caused by the temperature dependence of Young's modulus of Ag sintered layer. We also clarified that the maximum stress point in the whole system is at the corner of Ag sintered bonding layer at low temperatures, and shifts to the chip center for both SiC/Si structures as Ta increases.