TY - GEN
T1 - Weight Least Square Filter for Improving the Quality of Depth Map on FPGA
AU - Mao, Renzhi
AU - Wei, Kaijie
AU - Amano, Hideharu
AU - Kuno, Yuki
AU - Arai, Masatoshi
N1 - Funding Information:
VI. ACKNOWLEDGEMENT This work was partially supported by JST CREST Grant Number JPMJCR19K1, Japan.
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - The techniques based on measuring the distance between objects and the camera itself have made progress in recent years. Through this technology, the system used for 3D imaging will provide a great convenience for people's lives. In this project, we focus on optimizing depth maps with better quality for the 3D scene display system on the car. During the 3D imaging process, to calculate the distance between a certain location and one of the specific points of the scene, it will produce two depth maps computed from two images as an intermediate product for 3D imaging processing. However, there is a great number of invalid pixels that distance cannot be measured. In dealing with such drawbacks, post-filtering has been introduced as a solution. In this project, we propose implementing the Weight Least Square (WLS) filter on FPGA, which can fill the invalid pixels by using the results of neighboring pixels. Through our approach, we can improve the quality of the depth map on M-KUBOS. Besides that, the optimized memory usage can successfully suit the size of the memory on-chip, and a 69.29% acceleration compared to the ARM core.
AB - The techniques based on measuring the distance between objects and the camera itself have made progress in recent years. Through this technology, the system used for 3D imaging will provide a great convenience for people's lives. In this project, we focus on optimizing depth maps with better quality for the 3D scene display system on the car. During the 3D imaging process, to calculate the distance between a certain location and one of the specific points of the scene, it will produce two depth maps computed from two images as an intermediate product for 3D imaging processing. However, there is a great number of invalid pixels that distance cannot be measured. In dealing with such drawbacks, post-filtering has been introduced as a solution. In this project, we propose implementing the Weight Least Square (WLS) filter on FPGA, which can fill the invalid pixels by using the results of neighboring pixels. Through our approach, we can improve the quality of the depth map on M-KUBOS. Besides that, the optimized memory usage can successfully suit the size of the memory on-chip, and a 69.29% acceleration compared to the ARM core.
KW - 3D Image Processing
KW - Computer Graphics
KW - FPGA
KW - Smoothing Filter
KW - WLS
UR - http://www.scopus.com/inward/record.url?scp=85124156868&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85124156868&partnerID=8YFLogxK
U2 - 10.1109/CANDARW53999.2021.00056
DO - 10.1109/CANDARW53999.2021.00056
M3 - Conference contribution
AN - SCOPUS:85124156868
T3 - Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021
SP - 297
EP - 300
BT - Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th International Symposium on Computing and Networking Workshops, CANDARW 2021
Y2 - 23 November 2021 through 26 November 2021
ER -